1) Field of the Invention
This invention relates generally to a structure and fabrication of a semiconductor memory device and more particularly to the structure and fabrication of a butting contact structure between conductive layers and the substrate in a semiconductor device having a shallow trench isolation (STI).
2) Description of the Prior Art
There is a trend in the semiconductor industry toward fabricating larger and more complex functions on a given semiconductor chip. The larger and more complex functions are achieved by reducing device sizes and spacing and by reducing the junction depth of regions formed in the semiconductor substrate. Among the feature sizes which are reduced in size are the width and spacing of interconnecting metal lines and the contact openings through which the metallization makes electrical contact to device regions. As the feature sizes are reduced, new problems arise which must be solved in order to economically and reliably produce the semiconductor devices.
As the contact size and junction depth are reduced, a new device contact process is required to overcome the problems which are encountered.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,330,929 (Pfiester et al.) which shows a method of making a 6 T SRAM Cell. U.S. Pat No. 5,451,534 (Yang) shows a method of making a single layer TFT 6 T SRAM. U.S. Pat. No. 5,394,358 (Huang) shows a method of forming a 6 T SRAM that reduces the number of local interconnections. In addition, Wolf, "Silicon Processing For The VISI Era: Vol. 2", on pp. 160 to 164, discusses butted Contacts and Buried contacts.
However, there is still a need for an improved butting contact structure.